1. Field of the Invention
The present invention relates generally to offset compensation, and more particularly to offset compensation using non-uniform calibration.
2. Background Art
Device mismatch due to process and/or temperature variations can significantly affect the performance of analog and/or digital circuits. For instance, due to process variations, identically designed components (e.g., NMOS transistors, PMOS transistors, etc.) can have different geometry and/or electrical characteristics, even when located proximately to each other on the same silicon wafer. Consequently, a device formed using such components will have an inherent offset relative to an actual prototype, resulting in a degradation in the device performance.
One way to reduce the effects of device mismatch is by increasing the device size, thereby making component variations less significant. However, this correspondingly results in increased hardware complexity, circuit area, and cost.
Accordingly and since device mismatch is generally very difficult to avoid, offset compensation is another way to deal with device mismatch problems.
What is needed therefore are methods and systems for compensating for offset due to device mismatch.